Current FIN field-effect transistor (FINFET) process flows often employ sidewall image transfer (SIT) patterning to produce fins at a pitch beyond that achievable using standard lithography. A conventional SIT process generally involves use of a sacrificial mandrel (typically formed from amorphous silicon) to place spacers. Once the mandrel is removed, the spacers can be used as a hardmask to pattern the fins.
Removing the mandrel selective to the underlying substrate can, however, be a challenge. For instance, if the substrate is also formed from silicon, then removal of the mandrel without affecting the substrate is difficult. To solve this problem, a planarizing layer can be deposited onto the substrate, covering the mandrel, and then recessed to expose a top of the mandrel. The planarizing layer will protect the underlying substrate during mandrel removal. However, successful implementation of this scheme in an SIT process flow requires fine tuning of the density of the planarizing material which is oftentimes difficult to control.
Therefore improved SIT pattering processes would be desirable.